| ASIC and FPGA Verification: A Guide to Component Modeling Contributor(s): Munden, Richard (Author) |
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ISBN: 0125105819 ISBN-13: 9780125105811 Publisher: Morgan Kaufmann Publishers OUR PRICE: $73.21 Product Type: Paperback - Other Formats Published: September 2004 Annotation: Richard Munden demonstrates how to create and use simulation models for verifying ASIC and FPGA designs and board-level designs that use off-the-shelf digital components. Based on the VHDL/VITAL standard, these models include timing constraints and propagation delays that are required for accurate verification of today??'s digital designs. ASIC and FPGA Verification: A Guide to Component Modeling expertly illustrates how ASICs and FPGAs can be verified in the larger context of a board or a system. It is a valuable resource for any designer who simulates multi-chip digital designs. *Provides numerous models and a clearly defined methodology for performing board-level simulation. *Covers the details of modeling for verification of both logic and timing. *First book to collect and teach techniques for using VHDL to model "off-the-shelf" or "IP" digital components for use in FPGA and board-level design verification. |
| Additional Information |
| BISAC Categories: - Computers | Systems Architecture - General - Technology & Engineering | Electronics - Digital - Technology & Engineering | Electronics - Microelectronics |
| Dewey: 621.381 |
| LCCN: 2004557557 |
| Series: Systems on Silicon |
| Physical Information: 0.92" H x 7.68" W x 9.48" (1.80 lbs) 336 pages |
| Descriptions, Reviews, Etc. |
| Publisher Description: Richard Munden demonstrates how to create and use simulation models for verifying ASIC and FPGA designs and board-level designs that use off-the-shelf digital components. Based on the VHDL/VITAL standard, these models include timing constraints and propagation delays that are required for accurate verification of today's digital designs. ASIC and FPGA Verification: A Guide to Component Modeling expertly illustrates how ASICs and FPGAs can be verified in the larger context of a board or a system. It is a valuable resource for any designer who simulates multi-chip digital designs. |