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Analysis and Design of CMOS Clocking Circuits for Low Phase Noise
Contributor(s): Bae, Woorham (Author), Jeong, Deog-Kyoon (Author)
ISBN: 1785618016     ISBN-13: 9781785618017
Publisher: Institution of Engineering & Technology
OUR PRICE:   $147.25  
Product Type: Hardcover
Published: August 2020
Qty:
Additional Information
BISAC Categories:
- Technology & Engineering | Electronics - Circuits - Integrated
- Computers | Computer Engineering
Dewey: 621.397
LCCN: 2020414435
Physical Information: 0.7" H x 6.2" W x 9.4" (1.25 lbs) 256 pages
 
Descriptions, Reviews, Etc.
Publisher Description:

As electronics continue to become faster, smaller and more efficient, development and research around clocking signals and circuits has accelerated to keep pace. This book bridges the gap between the classical theory of clocking circuits and recent technological advances, making it a useful guide for newcomers to the field, and offering an opportunity for established researchers to broaden and update their knowledge of current trends.

The book begins by introducing the theory of Fourier transform and power spectral density, then builds on this foundation in chapter 2 to define phase noise and jitter. Chapter 3 discusses the theory and primary implementation of CMOS oscillators, including LC oscillators and ring oscillators, and chapter 4 introduces techniques for analysing their phase noise and jitter. Chapters 5-7 cover conventional clocking circuits; phase-locked loop (PLL) and delay-locked loop (DLL), which suppress the phase noise of CMOS oscillators. The building blocks of conventional PLLs/DLLs are described, and the dynamics of the PLL/DLL negative feedback loop explored in depth, with practical design examples. Chapters 8-11 address state-of-the-art circuit techniques for phase noise suppression, presenting the principles and practical issues in circuit implementation of sub-sampling phase detection techniques, all-digital PLL/DLL, injection-locked oscillator, and clock multiplying DLL. Extensive survey and discussion on state-of-the-art clocking circuits and benchmarks are covered in an Appendix.