| A Bit-Serial Implementation of the AES Encryption Algorithm Contributor(s): Weber, Raphael (Author) |
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ISBN: 3639327136 ISBN-13: 9783639327137 Publisher: VDM Verlag OUR PRICE: $50.27 Product Type: Paperback Published: January 2011 |
| Additional Information |
| BISAC Categories: - Computers | Hardware - General |
| Physical Information: 0.28" H x 6" W x 9" (0.41 lbs) 120 pages |
| Descriptions, Reviews, Etc. |
| Publisher Description: In this work we describe how to implement the Advanced Encryption Standard (AES) for a bit-serial fully pipelined architecture. This is possible through a requirements analysis and extension of the architecture. For the AES design, we rely on a high level synthesis tool to automatically generate the AES algorithm's elements. In addition to the implementation of the AES cipher, we describe a low- level space optimization approach to reduce the hardware utilization of our AES design. This involves a register transfer level analysis of the architecture's operators. The resulting correctly operating AES implementation was shrunk by about 25% through our optimization. |