| Wafer Level 3-D ICS Process Technology 2009 Edition Contributor(s): Tan, Chuan Seng (Editor), Gutmann, Ronald J. (Editor), Reif, L. Rafael (Editor) |
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ISBN: 0387765328 ISBN-13: 9780387765327 Publisher: Springer OUR PRICE: $161.49 Product Type: Hardcover - Other Formats Published: September 2008 Annotation: This book focuses on foundry-based process technology that enables the fabrication of 3-D ICs. The core of the book discusses the technology platform for pre-packaging wafer lever 3-D ICs. However, this book does not include a detailed discussion of 3-D ICs design and 3-D packaging. This is an edited book based on chapters contributed by various experts in the field of wafer-level 3-D ICs process technology. They are from academia, research labs and industry. |
| Additional Information |
| BISAC Categories: - Technology & Engineering | Electronics - Microelectronics - Technology & Engineering | Engineering (general) - Technology & Engineering | Optics |
| Dewey: 621.381 |
| LCCN: 2008920894 |
| Series: Integrated Circuits and Systems |
| Physical Information: 0.9" H x 6.2" W x 9.3" (1.45 lbs) 410 pages |
| Descriptions, Reviews, Etc. |
| Publisher Description: Three-dimensional (3D) integration is clearly the simplest answer to most of the semiconductor industry's vexing problems: heterogeneous integration and red- tions of power, form factor, delay, and even cost. Conceptually the power, latency, and form factor of a system with a ?xed number of transistors all scale roughly linearly with the diameter of the smallest sphere enclosing frequently interacting devices. This clearly provides the fundamental motivation behind 3D technologies which vertically stack several strata of device and interconnect layers with high vertical interconnectivity. In addition, the ability to vertically stack strata with - vergent and even incompatible process ?ows provides for low cost and low parasitic integration of diverse technologies such as sensors, energy scavengers, nonvolatile memory, dense memory, fast memory, processors, and RF layers. These capabilities coupled with today's trends of increasing levels of integrated functionality, lower power, smaller form factor, increasingly divergent process ?ows, and functional diversi?cation would seem to make 3D technologies a natural choice for most of the semiconductor industry. Since the concept of vertical integration of different strata has been around for over 20 years, why aren't vertically stacked strata endemic to the semiconductor industry? The simple answer to this question is that in the past, the 3D advantages while interesting were not necessary due to the tremendous opportunities offered by geometric scaling. In addition, even when the global interconnect problem of high-performance single-core processors seemed insurmountable without inno- tions such as 3D, alternative architectural solutions such as multicores could eff- tivelydelaybutnoteliminatetheneedfor3D. |