| Layout Optimization in VLSI Design 2001 Edition Contributor(s): Bing Lu (Editor), Ding-Zhu Du (Editor), Sapatnekar, S. (Editor) |
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ISBN: 1402000898 ISBN-13: 9781402000898 Publisher: Springer OUR PRICE: $161.49 Product Type: Hardcover - Other Formats Published: December 2001 Annotation: The exponential scaling of feature sizes in semiconductor technologies has side-effects on layout optimization, related to effects such as interconnect delay, noise, crosstalk, signal integrity, parasitics effects, and power dissipation, that invalidate the assumptions that form the basis of previous design methodologies and tools. This book is intended to sample the most important, contemporary, and advanced layout optimization problems emerging with the advent of very deep submicron technologies in semiconductor processing. Audience: A reference work for graduate students, senior undergraduates, and researchers. |
| Additional Information |
| BISAC Categories: - Technology & Engineering | Electrical - Technology & Engineering | Electronics - Circuits - Vlsi & Ulsi - Computers | Logic Design |
| Dewey: 621.395 |
| LCCN: 2001050273 |
| Series: Network Theory and Applications |
| Physical Information: 0.73" H x 6.56" W x 9.7" (1.47 lbs) 288 pages |
| Descriptions, Reviews, Etc. |
| Publisher Description: Introduction The exponential scaling of feature sizes in semiconductor technologies has side-effects on layout optimization, related to effects such as inter- connect delay, noise and crosstalk, signal integrity, parasitics effects, and power dissipation, that invalidate the assumptions that form the basis of previous design methodologies and tools. This book is intended to sample the most important, contemporary, and advanced layout opti- mization problems emerging with the advent of very deep submicron technologies in semiconductor processing. We hope that it will stimulate more people to perform research that leads to advances in the design and development of more efficient, effective, and elegant algorithms and design tools. Organization of the Book The book is organized as follows. A multi-stage simulated annealing algorithm that integrates floorplanning and interconnect planning is pre- sented in Chapter 1. To reduce the run time, different interconnect plan- ning approaches are applied in different ranges of temperatures. Chapter 2 introduces a new design methodology - the interconnect-centric design methodology and its centerpiece, interconnect planning, which consists of physical hierarchy generation, floorplanning with interconnect planning, and interconnect architecture planning. Chapter 3 investigates a net-cut minimization based placement tool, Dragon, which integrates the state of the art partitioning and placement techniques. |