| Full-Chip Nanometer Routing Techniques 2007 Edition Contributor(s): Ho, Tsung-Yi (Author), Chang, Yao-Wen (Author), Chen, Sao-Jie (Author) |
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ISBN: 1402061943 ISBN-13: 9781402061943 Publisher: Springer OUR PRICE: $104.49 Product Type: Hardcover - Other Formats Published: August 2007 Annotation: At 90 nm, wires account for nearly 75% of the total delay in a circuit. Even more insidious, however, is that among nearly 40% of these nets, more than 50% of their total net capacitance are attributed to the cross-coupling capacitance between neighboring signals. At this point a new design and optimization paradigm based on real wires is required. Nanometer routers must prevent and correct these effects on-the-fly in order to reach timing closure. From a manufacturability standpoint, nanometer routers must explicitly deal with the ever increasing design complexity, and be capable of adapting to the constraint requirements of timing, signal integrity, process antenna effect, and new interconnect architecture such as X-architecture. In the nanometer era, we must look into new-generation routing technologies that combine high performance and capacity with the integration of congestion, timing, SI prevention, and DFM algorithms as the best means of getting to design closure quickly. In this book, we present a novel multilevel full-chip router, namely mSIGMA for SIGnal-integrity and MAnufacturability optimization. And these routing technologies will ensure faster time-to-market and time-to-profitability. |
| Additional Information |
| BISAC Categories: - Technology & Engineering | Electronics - Circuits - General - Technology & Engineering | Nanotechnology & Mems - Computers | Cad-cam |
| Dewey: 620.004 |
| Series: Analog Circuits and Signal Processing |
| Physical Information: 0.31" H x 6.14" W x 9.21" (0.78 lbs) 102 pages |
| Descriptions, Reviews, Etc. |
| Publisher Description: This book presents a novel multilevel full-chip router, namely mSIGMA for SIGnal-integrity and MAnufacturability optimization. These routing technologies will ensure faster time-to-market and time-to-profitability. The book includes a detailed description on the modern VLSI routing problems, and multilevel optimization on routing design to solve the chip complexity problem. |