| Verification by Error Modeling: Using Testing Techniques in Hardware Verification 2003 Edition Contributor(s): Radecka, Katarzyna (Author), Zilic, Zeljko (Author) |
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ISBN: 1402076525 ISBN-13: 9781402076527 Publisher: Springer OUR PRICE: $104.49 Product Type: Hardcover - Other Formats Published: November 2003 Annotation: Verification presents the most time-consuming task in the integrated circuit design process. The increasing similarity between implementation verification and the ever-needed task of providing vectors for manufacturing fault testing is tempting many professionals to combine verification and testing efforts. This book presents the basis for reusing the test vector generation and simulation for the purpose of implementation verification, to result in a significant timesaving. The book brings the results in the direction of merging manufacturing test vector generation and verification. It first discusses error fault models suitable for approaching the verification by testing methods. Then, it elaborates a proposal for an implicit fault model that uses the Arithmetic Transform representation of a circuit and the faults. Presented is the fundamental link between the error size and the test vector size, which allows parametrizable verification by test vectors. Furthermore, the test vector set is sufficient not only for detecting, but also for diagnosing and correcting the design errors. The practical use of any such simulation-based verification scheme can be seriously impaired by redundant faults, that otherwise require exhaustive simulations. The redundant fault identification methods are presented that are well suited for the type of faults considered. Finally, the same representation can be used to augment and expand the formal verification schemes that are to be used in conjunction with the simulation-based verification. The primary audience for Verification by Error Modeling includes researchers in verification and testing, managers in charge of verification of test andpracticing engineers. Due to its comprehensive coverage of background topics, the book can also be used for teaching courses on verification and test topics. |
| Additional Information |
| BISAC Categories: - Technology & Engineering | Electronics - Circuits - General - Computers | Logic Design - Technology & Engineering | Electrical |
| Dewey: 621.395 |
| LCCN: 2003062044 |
| Series: Frontiers in Electronic Testing |
| Physical Information: 0.6" H x 6.46" W x 9.76" (1.21 lbs) 216 pages |
| Descriptions, Reviews, Etc. |
| Publisher Description: 1. DESIGN FLOW Integrated circuit (IC) complexity is steadily increasing. ICs incorporating hundreds of millions of transistors, mega-bit memories, complicated pipelined structures, etc., are now in high demand. For example, Intel Itanium II processor contains more than 200 million transistors, including a 3 MB third level cache. A billion transistor IC was said to be "imminently doable" by Intel fellow J. Crawford at Microprocessor Forum in October 2002 40]. Obviously, designing such complex circuits poses real challenges to engineers. Certainly, no relief comes from the competitive marketplace, with increasing demands for a very narrow window of time (time-to-market) in engineering a ready product. Therefore, a systematic and well-structured approach to designing ICs is a must. Although there are no widely adhered standards for a design flow, most companies have their own established practices, which they follow closely for in-house design processes. In general, however, a typical product cycle includes few milestones. An idea for a new product starts usually from an - depth market analysis of customer needs. Once a window of opportunity is found, product requirements are carefully specified. Ideally, these parameters would not change during the design process. In practice, initial phases of preparing a design specification are susceptible to potential errors, as it is very difficult to grasp all the details in a complex design. |