Logic Synthesis for Finite State Machines Based on Linear Chains of States: Foundations, Recent Developments and Challenges 2018 Edition Contributor(s): Barkalov, Alexander (Author), Titarenko, Larysa (Author), Bieganowski, Jacek (Author) |
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ISBN: 3319598368 ISBN-13: 9783319598369 Publisher: Springer OUR PRICE: $104.49 Product Type: Hardcover - Other Formats Published: July 2017 |
Additional Information |
BISAC Categories: - Computers | Intelligence (ai) & Semantics - Technology & Engineering | Electronics - Circuits - General - Technology & Engineering | Engineering (general) |
Dewey: 006.3 |
Series: Studies in Systems, Decision and Control |
Physical Information: 0.56" H x 6.14" W x 9.21" (1.12 lbs) 225 pages |
Descriptions, Reviews, Etc. |
Publisher Description: This book discusses Moore finite state machines (FSMs) implemented with field programmable gate arrays (FPGAs) including look-up table (LUT) elements and embedded memory blocks (EMBs). To minimize the number of LUTs in FSM logic circuits, the authors propose replacing a state register with a state counter. They also put forward an approach allowing linear chains of states to be created, which simplifies the system of input memory functions and, therefore, decreases the number of LUTs in the resulting FSM circuit. The authors combine this approach with using EMBs to implement the system of output functions (microoperations). This allows a significant decrease in the number of LUTs, as well as eliminating a lot of interconnections in the FSM logic circuit. As a rule, it also reduces the area occupied by the circuit and diminishes the resulting power dissipation. This book is an interesting and valuable resource for students and postgraduates in the area of computer science, as well as for designers of digital systems that included complex control units |