| Architectural Optimizations in Multi-Core Processors Contributor(s): Fide, Sevin (Author) |
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ISBN: 363910157X ISBN-13: 9783639101577 Publisher: VDM Verlag OUR PRICE: $60.53 Product Type: Paperback Published: November 2008 |
| Additional Information |
| BISAC Categories: - Computers | Computer Engineering |
| Physical Information: 0.31" H x 6" W x 9" (0.44 lbs) 144 pages |
| Descriptions, Reviews, Etc. |
| Publisher Description: The quest for greater computational power is never-ending. Recently, the architectural trend has shifted from improving single-threaded application performance to improving multi-threaded application per-formance. Thus, multi-core processors have been increasingly popular. To achieve concurrent execution of threads on multi-core processors, applications must be explicitly restructured to exploit parallelism, either by programmers or compilers. However, conventional parallel pro-gramming models may introduce overhead due to synchronization and communications among threads in multi-threaded applications. This book presents three architectural optimizations to improve thread-based synchronization and communications support in multi-core processors. Register-Based Synchronization (RBS) uses hardware registers efficiently to provide synchronization support in multi-core processors. Prepushing is a software controlled data forwarding technique to provide communications support in multi-core processors. Software Controlled Eviction (SCE) improves shared cache communications by placing shared data in shared caches. |